In recent years, an all digital phase locked loop (ADPLL) circuit has been widely used for purposes such as clock generation in various types of large scale integration (LSI) and a local oscillator of a radio frequency (RF) system. Many of components of the ADPLL circuit are constituted by digital circuits and, as compared with an analog phase locked loop (PLL) using a conventional charge pump and a voltage controlled oscillator (VCO), the ADPLL circuit can attain high performance with a compact area and low power and is characterized by easy application to a minute process.
As a technology related to the ADPLL circuit, for example, Patent Document 1 and Patent Document 2 are disclosed. Both of these Patent Documents 1 and 2 use a configuration in which integer information (integer phase) of a feedback phase is obtained by a counter driven by a feedback clock signal and fractional information (fractional phase) finer than a feedback clock period is obtained by a time-to-digital converter (TDC) constituted by a delay line and a flip-flop (refer to FIGS. 1 and 5 of Patent Document 1 and FIG. 1 of Patent Document 2).